Static Timing Analysis

Project : HelloWorld_Blinky01
Build Time : 08/14/13 16:04:29
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.50
Vddd : 5.50
Vio0 : 5.50
Vio1 : 5.50
Vio2 : 5.50
Vio3 : 5.50
Voltage : 5.5
Vusb : 5.50
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(fixed-function) Clock_1(fixed-function) 250.000  Hz 250.000  Hz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyMASTER_CLK 250.000  Hz 250.000  Hz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A